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CTR: DoD Microelectronics: Field Programmable Gate Array Best Practices – Threat Catalog (May 2024 Update) ↗ source

May 13, 2024 NSA Analysis Report

Summary

Cybersecurity Technical Report Best Practices – Threat Catalog National Security Agency | Cybersecurity Technical Report DoD Microelectronics: FPGA Best Practices – Threat Catalog This document was created through collaboration with each of the JFAC labs: National Security Agency (NSA), Air Force Research Lab (AFRL) RYDT, Naval Surface Warfare Center (NSWC) Crane, and Army Development Command (DEVCOM)/AVMC. For additional information, guidance, or assistance with this document, please contact the Joint Federated Assurance Center U/OO/156779-24 | PP-24-1961 | May 2024 Ver. 1.1 ii National Security Agency | Cybersecurity Technical Report DoD Microelectronics: FPGA Best Practices – Threat Catalog Disclaimer of warranties and endorsement The information and opinions contained in this document are provided "as is" and without any warranties or guarantees. Reference herein to any specific commercial products, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement, recommendation, or favoring by the United States Government, and this guidance shall not be used for advertising or product Joint Federated Assurance Center This document was developed in furtherance of NSA’s cybersecurity missions.

News Coverage

No coverage found in monitored research blogs or news feeds.

CVEs Referenced in This Publication

No CVEs are referenced in this publication.

Vendors Named in This Publication

No KEV-catalogued vendors are named in this publication.